rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD6140 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998 bandpass sd if subsystem functional block diagram mixer post amplifier mixer d modulator agc detector circuit ecl-to-cmos level-shifter lna bias amplifier preamplifier if_input lna_sense lna_force d _data_out d _clock_out buffer_vdd clk_in+ clk_inC buffer_gnd avdd agnd dgnd dvdd power_down agc_capacitor 0.1 m f bias_resistor 39k v r int bias system agc_tc_select voltage_reference_in AD6140 lo_in+ lo_inC features if subsystem bandpass sd modulator variable-gain preamplifier with 13 db of agc range mixer agc detector op amp for lna biasing ecl-to-cmos level translator ultralow power design 2.7 v operating voltage 4.8 ma current consumption power-down control small 20-lead ssop package applications flex?, reflex? receivers multimode receivers general description the AD6140 is a bandpass sd adc if ic for receivers requiring a high dynamic range and multiple filter bandwidths. with an external decimation filter, it creates a multibit analog-to-digital converter. the AD6140 consists of a variable gain, low noise preamplifier, mixer, agc detector, bandpass sd modulator, an ecl-to-cmos level translator for the system clock, and an auxiliary amplifier for use in biasing a discrete lna. it is de- signed to operate with motorolas reflex chipset solution. contact motorola directly for more information about the reflex chipset solution. with data and clock o utputs at cmos logic levels, it interfaces to an external decimation filter. it comes in a 20-lead plastic ssop and op erates over the C40 c to +85 c industrial temperature range at 2.7 v. flex and reflex are trademarks of motorola, inc.
rev. 0 C2C AD6140Cspecifications (t a = +25 8 c, v cc = 2.7 v, voltage_reference_in = 1 v, unless otherwise noted) specification conditions min typ max units overall voltage_reference_in = 1 v 5% dc, if = 49.6 mhz lo = 49.792 mhz or 49.408 mhz, 200 mv p-p differential input clock = 6.144 mhz, 800 mv p-p differential ecl input, clock asymmetry = 50 2.5% input third order intercept point at max gain C27 C19 dbm noise figure at max gain, external termination 10.5 db input resistance at if_input (pin 19) 2.5 k w input capacitance at if_input (pin 19) 12 pf dynamic range 6.25 khz bandwidth centered at 192 khz 76 83 db maximum gain 29.5 db minimum gain 16 db agc detector agc threshold C24 dbm capacitor charging current agc_tc_select input = logic low (fast agc) 2.8 m a agc_tc_select input = logic high (slow agc) 50 na ecl-to-cmos level vdd (to vdd C 0.8 v) differential levels translator clock output drive 5 pf load 2.6 v p-p clock asymmetry 5 pf load 2.5 % lna bias amplifier voltage lna_force 2.9 v lna_sense, minimum gain 1.7 v lna_sense input voltage range vdd vdd C 0.3 v power-down interface logic threshold 0.7 v turn-on response time to valid data output 100 m s turn-off response time to typical power-down supply current 100 m s power supply supply voltage 2.5 2.9 v supply current power-down input: logic low = on, if_input = 0 v 4.8 5.75 ma power-down current power-down input: logic high = off 3 m a operating temperature range C40 +85 c specifications subject to change without notice.
rev. 0 AD6140 C3C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD6140 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1 supply voltage to ground . . . . . . . . . . . . . . . . . . . . . . +5.5 v internal power dissipation 2 . . . . . . . . . . . . . . . . . . . . 50 mw operating temperature range . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature, soldering (60 sec) . . . . . . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended rating conditions for extended periods may affect device reliability. 2 thermal characteristics: 20-lead ssop: q ja = 126 c/w. pin configuration top view (not to scale) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 AD6140 agc tc select power down buffer vdd lna sense clk in+ clk inC d clock out d data out buffer gnd dvdd dgnd agc capacitor if input agnd voltage reference in lo in+ lo inC bias resistor lna force avdd ordering guide temperature package package model range description option AD6140ars C40 c to +85 c shrink small outline package rs-20 AD6140arsrl C40 c to +85 c 20-lead plastic ssop on tape-and-reel
rev. 0 AD6140 C4C pin function description pin pin no name function applicable signal levels 1 lna_force output for biasing discrete lna output ranges from 0 v (lna off) to 2.7 v 2 lna_sense input for biasing discrete lna vdd to vdd C 0.3 v input 3 clk_in+ positive 6.144 mhz adc clock input 800 mv p-p differential input vdd to vdd C 0.8 v levels direct coupled into 1500 w impedance 4 clk_inC negative 6.144 mhz adc clock input 800 mv p-p differential input vdd to vdd C 0.8 v levels direct coupled into 1500 w impedance 5 buffer_gnd ecl-to-cmos level translator ground pin connected to ground 6sd _data_out sd adc serial data output cmos logic levels 7sd _clock_out 6.144 mhz adc clock output cmos logic levels 8 buffer_vdd ecl-to-cmos level translator vdd digital supply input 9 power_down turns ic off and on cmos logic levels; 0 v = on, vpos = off 10 agc_tc_select agc time constant select; changes cmos logic levels; 0 v = fast mode, agc capacitor charging current by 56:1, vpos = slow mode where fast agc current is 56 slow agc current 11 dvdd digital power supply input pin connected to digital supply 12 dgnd digital ground pin connected to ground 13 agc_capacitor charge/discharge current into agc agc integration capacitor integrator capacitor connected to ground 14 lo_in+ positive lo input 200 mv p-p differential input; internally ac-coupled into 1500 w impedance 15 lo_inC negative lo input 200 mv p-p differential input, internally ac-coupled into 1500 w impedance 16 bias_resistor resistor to ground sets overall bias 39 k w resistor connected to ground current and power consumption 17 voltage_reference_in adc voltage reference input regulated and filtered 1.0 v 5% input 18 agnd analog ground pin connected to ground 19 if_input if input typically 16.4 m v p-p to 65.2 mv p-p 20 avdd analog power supply input pin connected to analog supply
rev. 0 AD6140 C5C temperature C 8 c 12 10 8 C40 noise figure C db 11 9 C20 25 60 85 v cc = +2.7v figure 1. noise figure vs. temperature supply voltage C volts 12.0 11.0 10.0 2.5 noise figure C db 11.5 10.5 2.6 2.7 2.8 2.9 t = +25 8 c figure 2. noise figure vs. power supply supply voltage C volts C19.20 2.5 input ip3 C dbm 2.6 2.7 2.8 2.9 C19.25 C19.30 C19.35 C19.40 C19.45 C19.50 C19.55 C19.60 C19.65 figure 3. input ip3 vs. power supply typical performance characteristicsC temperature C 8 c C21.0 C40 input ip3 C dbm 25 85 C20.5 C20.0 C19.5 C19.0 C18.5 C18.0 C17.5 C17.0 C16.5 C16.0 figure 4. input ip3 vs. temperature \ if input level C dbm 60 20 0 C120 snr C db 30 10 C112 C108 C100 C90 C80 C70 C60 C50 C40 C30 C23 C19 40 50 figure 5. signal to noise ratio vs. if input level at t a = +25 c temperature C 8 c 4.9 4.7 C40 current C ma 4.8 C20 25 60 85 v cc = +2.7v figure 6. supply current vs. temperature
rev. 0 AD6140 C6C power supply voltage C volts 5.2 4.8 4.4 2.5 current C ma 5.0 4.6 2.6 2.7 2.8 2.9 t a = +25 8 c figure 7. supply current vs. power supply voltage mixer post amplifier mixer d modulator agc detector circuit ecl-to-cmos level-shifter lna bias amplifier preamplifier if_input lna_sense lna_force d _data_out d _clock_out buffer_vdd clk_in+ clk_inC buffer_gnd avdd agnd dgnd dvdd power_down agc_capacitor 0.1 m f bias_resistor 39k v r int bias system agc_tc_select voltage_reference_in AD6140 lo_in+ lo_inC figure 8. functional block diagram sd modulation a sd modulator uses feedback around a low noise quantizer (1 bit in this case) in order to shape the spectrum of quantiza- tion noise. using this technique, we can shape noise away from an arbitrary passband, within which we can place a modulated signal. a sd modulator reproduces the input, but adds quanti- zation noise, which can be digitally removed with a filter, known as a decimation filter. applying this technique to bandpass signals results in an analog-to-digital converter suitable for converting the if signals in a digital radio. the output of the AD6140s sd modulator is shown in figure 9. as can be seen, the noise is shaped away from a narrow band- width, within which we place a signal (a sine wave in this case) resulting in a narrowband, high dynamic range digital represen- tation of the analog input. frequency C khz 0 C100 C150 0 output level C db C50 500 1000 1500 2000 2500 3000 3500 response from 0khz to (f s /2)khz figure 9. output spectrum of AD6140 product overview the AD6140 is a bandpass sd analog-to-digital con verter if ic for dual conversion receivers requiring a high dynamic range and multiple filter bandwidths. it consists of a variable gain, low noise preamplifier, mixer, automatic gain control (agc) detec- tor, bandpass sd modulator, an ecl to cmos level translator and an auxiliary amplifier for use in biasing a discrete lna. the low noise preamplifier accepts a first if input at 49.6 mhz from 16.4 m v p-p to 63.2 mv p-p. it provides a variable gain from 12 db to 25 db. the mixer accepts an lo frequency of 49.792 mhz or 49.408 mhz, resulting in an if frequency of 192 khz. the lo level should be 200 mv p-p differential. it is ac-coupled to the AD6140. the mixer operates in the linear region, hence the gain of the mixer is a function of the lo level. as a result, spe- cial care must be taken to ensure that the lo level is 200 mv p-p,
rev. 0 AD6140 C7C other wise, the expected gain will not be obtained from the AD6140. in addition to the mixer, there is a mixer post- amplifier within the AD6140. the total gain from the mixer and mixer post-amplifier is 5 db. the sd modulator uses a 6.144 mhz clock, which is a differen- tial ecl input. there is an ecl-to-cmos converter on the AD6140, which converts this differential ecl input into a single-ended cmos signal. this 6.144 mhz single-ended cmos clock is provided at pin 7 ( sd _clock_out). the output data of the AD6140 is a 6.144 mhz single bitstream at pin 6 ( sd _data_out). the signal gain through the sd modulator is C0.77 db. within the sd modulator, the data output digital bitstream is fed through a 1-bit d/a converter and is fed back to numerous internal points. the level of this feedback signal, known as the full-scale level, defines the sd modulator input signal level, which would result in the output digital bitstream containing the maximum number of ones possible. this condition, known as maximum ones density, represents the maximum in-band out- put signal power of the sd modulator. the full-scale level is set to 2 v p-p or C4.77 dbm (relative to 1500 w ). however, if a signal into the modulator is C4.77 dbm, the modulator will enter an unstable state. consequently, the maximum input to the modulator is constrained to 5 db less than the signal, which would produce maximum ones density. this level, defined as the clip level, is C9.77 dbm (relative to 1500 w ). the maximum signal into the modulator does not correspond to maximum ones density. the entire dynamic range of the result- ing analog to digital converter ( sd modulator plus decimation filter) is not realized. in order to relate the maximum signal into the modulator to the maximum signal out of the modulator, a gain of 5 db should be applied in the decimation filter. as can be seen in figure 5, the output signal to noise ratio will increase until a point at which it rapidly degrades. this point represents the input signal level where the sd modulator has become unstable. as a result, the maximum input signal level is constrained by the point at which it is so high that ins tability occurs in the modulator. dynamic range is defined as the differ- ence between the integrated noise floor (within a particular bandwidth) and the power in the output signal just before the sd modulator has become unstable. for a typical 6.25 khz bandwidth centered around 192 khz, the AD6140 has 83 db of dynamic range. in order to increase the range of useful input signals of the AD6140, an agc detector is employed which senses the input signal level to the sd modulator and adjusts the gain in the pream- plifier. the agc circuitry provides 13 db of automatic gain control range. the agc operates when the internal agc voltage is between 700 mv (minimum gain) and 1.55 v (maximum gain). this v oltage can be measured on the agc_capacitor pin (pin 13). the AD6140 can be configured with the chip powered up or down. in order to power the chip down, set pin power_down (pin 9) high. in order to power it up, set pin power_down (pin 9) low. finally, an auxiliary amplifier used for biasing an external dis- crete lna is provided with the AD6140. frequency plan the AD6140 and its sd modulator are designed for a specific frequency plan: a 6.144 mhz master clock, a 49.6 mhz first if input, and a 192 khz center frequency in the bandpass sd modulator. the local oscillator may use high-side or low-side injection. the specifications for the AD6140 are only valid for this frequency plan. any deviation from this frequency plan may result in degradation of the specified performance. furtherm ore, there are only specific frequency plans which will result in ac- ceptable performance for most applications. to avoid problems, do not change the frequency plan. using the AD6140 in this section, we will examine a few areas of special impor- tance and include a few general applications tips. as is true of any device operating in the if frequency range, special care must be taken in pc board layout. the location of the particular grounding points must be considered, with the objective of minimizing any unwanted signal coupling. specifically, care should be taken in the layout of the if and lo signal paths as well as the data and clock digital bit-streams. layout of these portions of the pc board require special attention in order to ensure that the high frequency portions of these signals do not couple into other signals in the system. in order to maintain balance in differential signal levels, be sure to keep short and equal length transmission lines. the power supplies should be decoupled to ensure a clean dc signal. special care should be taken with respect to ensuring that the buffer_vdd is especially clean and at the appropriate levels since the output in-band noise floor is particularly sensi- tive to this supply. the if input signal should be impedance matched and ac coupled. the imped ance looking into the if input pin is typi- cally a 2.5 k w resistance in parallel with a 12 pf capacitance. the 1 v reference signal should be regulated and filtered. the value of the bias_resistor (pin 16) is 39 k w . the bias resistor sets the current consumption of the AD6140. because the AD6140 was characterized with a 39 k w bias resistor, this is the only value for which the AD6140 specifications are guaran- teed. maximum current consumption is measured when the AD6140 is operating at maximum gain. the agc integration capacitor should be large enough to by- pass any externally-generated noise on the internal agc line to ground in addition to providing a path for the charging and discharging of the agc current. in the motorola reflex chipset solution, this capacitor is 0.1 m f. the agc time con- stant is switch-selectable with the agc_tc_select pin (pin 10). the agc time constant has a typical current ratio of 56:1 when in the fast mode relative to slow mode. the n ominal agc current in the fast (high current) position is 2.8 m a and in the slow (low current) position is 50 na. the agc time constant may be calculated from equation 1. t cv i = (1) where t is the agc time constant in seconds, c is the value of the agc capacitor in farads, v is the full-scale change in the agc voltage, and i is the charging current in amperes.
rev. 0 AD6140 C8C c3436C3C10/98 printed in u.s.a. level diagram figure 10 shows a simplified block diagram of the AD6140 with the expected signal levels for the minimum gain configuration. mixer post amplifier mixer local oscillator input 49.792mhz C16.3 dbm referred to 50 v d modulator agc detector circuit preamplifier if input f = 49.6mhz 60mv p-p d data out 378mv p-p at 192khz figure 10. level diagram outline dimensions dimensions shown in inches and (mm). 20-lead ssop (rs-20) 20 11 10 1 0.295 (7.50) 0.271 (6.90) 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) pin 1 seating plane 0.008 (0.203) 0.002 (0.050) 0.07 (1.78) 0.066 (1.67) 0.0256 (0.65) bsc 0.078 (1.98) 0.068 (1.73) 0.009 (0.229) 0.005 (0.127) 0.037 (0.94) 0.022 (0.559) 8 8 0 8 motorola reflex transceiver figure 11 shows a block diagram of the motorola reflex chipset solution including the AD6140. as can be seen, the AD6140 accepts an if input from a crystal filter at 49.6 mhz. the frequency synthesizer provides the 6.144 mhz clock, while the lo is also generated from the frequency synthesizer but is fed to the AD6140 via the i/q modulator. the if data output and the clock output both feed into the if data processor. the lna bias amplifier provides the agc voltage for the first lna in the receive path. the dc power is supplied from the power management chip. lna max847 pwr mgt 2.8v dv dd 2.7v av dd primary battery transmit power source tx/rx sw 2.4v hbt pa saw filter 929-941mhz sc-4344-a xtal filter 49.6mhz agc 1 watt 986-902mhz mc145181 frequency synthesizer trf9506 i/q modulator 76.8mhz ref clk if data clock AD6140 d a/d if data processor spi to reflex codec 6.144mhz sampling clk tx data figure 11. reflex transceiver block diagram
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